The present invention pertains to a device to detect the functioning of the read system of an EPROM or EEPROM memory cell.
Certain integrated circuits presently available on the market are made with an electrically programmable non-volatile memory in which, most usually, non-modifiable data are recorded. Now, the electrically programmable non-volatile memories used in these integrated circuits are generally memories of the EPROM or EEPROM type.
In memories of the above type, each data storage element or memory cell comprises a floating gate MOS transistor, which may be mainly of the FAMOS (floating gate avalanche injection MOS) or SAMOS (stacked gate avalanche injection MOS) type. The above MOS transistor has two states. For an N-channel MOS transistor, in a first state, no charge is trapped at the floating gate. There may be a conduction channel between the source and the drain. The transistor is then conductive and behaves like a closed switch. In a second state, electrons have been trapped at the floating gate. They prevent the creation of a conduction channel in the substrate between the source and the drain. In this case, the transistor is off and behaves like an open switch.
To programme a MOS transistor 1 of the type shown in FIG. 1B, voltages higher than the normal operating voltage are appropriately applied to the control gate 4 and the electrode 2 in such a way that the floating gate 5 absorbs and keeps a charge of electrons. This charge of electrons at the floating gate 5 raises the conduction threshold at the control gate 4 of the transistor, from the minimum threshold V.sub.T0 of the non-programmed transistors to a higher threshold voltage V.sub.T1, as shown in FIG. 1A which gives the graph of the operating characteristic of a SAMOS type floating gate transistor.
To read a memory thus programmed, a voltage Vcc, smaller than the threshold voltage V.sub.T1 of the programmed transistors but higher than the minimum voltage V.sub.T0 of the non-programmed transistors, must be applied to the control gate. This read voltage is used to ascertain that the transistor is on or off. As shown in FIG. 1B, in general, the transistor 1 is connected by the electrode 2 to a bit line 6 which is voltage biased by a generator. The other electrode 3 of the transistor is connected to the ground. The bit line 6 is also connected to a current sensor which is not shown. This sensor measures the current put through the line by the generator. If the memory cell has not been programmed, the transistor is on, and when the read voltage Vcc, which is higher than V.sub.T0, is applied, the transistor becomes saturated. A drop in current is detected on the sensor. In the second case, when the memory cell has been programmed, the charges are trapped at the floating gate of the transistor. The read voltage Vcc, applied to the control gate, is, in this case, in the opposite direction to the potential barrier created in the conduction channel by the charges stored in the floating gate. But this read voltage is then not enough to modify the conduction of the channel, and the transistor stays off. As a result, the sensor at the end of the bit line does not perceive the variation in current.
If, with the above memories, a voltage higher than the threshold voltage V.sub.T1 is used for the read voltage Vcc, regardless of whether the memory cells are programmed or not, a current drop is detected on the sensors. Consequently, all the memory cells are read as if they were not programmed. It is therefore possible to read programmed memory cells as if they were not programmed. To remove this disadvantage, circuits with EPROM or EEPROM should not function with read voltages that are higher than the threshold voltage V.sub.T1. Now, with currently available circuits, it is possible to apply a read voltage Vcc which is higher than the threshold voltage V.sub.T1, without in any way modifying the functioning of the circuit.
The purpose of the present invention is to remove these disadvantages by proposing a device which enables the circuit to function for a read voltage ranging from V.sub.T0 to V.sub.T1 and which modifies the functioning of the circuit for a voltage which is slightly higher than this read voltage but is lower than the threshold voltage V.sub.T1 of the programmed memory cells.